% A template showing Latex possibilities for providing datasheets

\documentclass[a4paper, 10pt, onecolumn]{article}

\newcommand {\documentname}{LaTeX documentation demonstrator template}
\newcommand {\documenthdrstring}{\textit{\textbf{\documentname}}}


\usepackage[left=2cm,right=2cm,top=2cm,bottom=2cm,bindingoffset=0cm]{geometry}

\usepackage{tikz}
\usepackage{ctex}
\usepackage{pgfplots}
\usepackage{pgfplotstable}

\usepackage[utf8]{inputenc}        

\usepackage[english]{babel} 
\usepackage{url}                	% optional for Internet Links

\usepackage{helvet}
\renewcommand{\familydefault}{\sfdefault}
\fontfamily{phv}\selectfont

%\usepackage{caption}
%\usepackage{lipsum}
\usepackage{boldline}
%\usepackage{tabularx}
%\usepackage{longtable}
\usepackage{xtab}
%\usepackage{adjustbox}
%\usepackage{ltxtable}
%\usepackage{supertabular}

\usepackage[
singlelinecheck=false, % <-- important
margin=3cm, % Caption hat jetzt 3cm Einrückung relativ zum Textrand
font=small,labelfont=bf, labelfont += it % Labels der Bild- bzw Tabellenunterschriften sind jetzt Fett Kursiv 
]{caption}

\usepackage{colortbl}               % color in tables
\usepackage{color}


\definecolor{burgund}{RGB}{106,42,50}
\definecolor{gray50}{gray}{0.5}
\definecolor{gray25}{gray}{0.75}
\definecolor{lightgray}{gray}{0.9}

\usepackage{graphicx}
\usepackage{lscape}

\usepackage{amsmath}                % optional for formulas
\usepackage{float}
%\usepackage[font=sf]{floatrow}

\usepackage{sectsty}
\allsectionsfont{\normalfont\sffamily\bfseries} 

%\usepackage{bytefield}


\usepackage{fancyhdr}
\pagestyle{fancy}
\fancypagestyle{title}{%
	\fancyhead{}
	\renewcommand{\headrulewidth}{0pt}
	\rhead{\includegraphics[width=4cm]{fig/smartFPGAlogo.png}}
	%\lhead{\ipcorename}
}
\setlength\headheight{46pt} %% just to make warning go away. Adjust the value after looking into the warning.
\rhead{\includegraphics[width=4cm]{fig/smartFPGAlogo.png}}
\lhead{\documenthdrstring}
\textheight = 695pt

\def\widehline{%
	\noalign{\global\dimen1 \arrayrulewidth
		\global\arrayrulewidth3\arrayrulewidth}%
	\hline
	\noalign{\global\arrayrulewidth\dimen1 }}

\newcommand{\chline}{%
	\arrayrulecolor{burgund}\widehline\arrayrulecolor{gray25}
}


\usepackage[
colorlinks=true,
urlcolor=blue,
linkcolor=black,
citecolor=black
]{hyperref}

\begin{document}
	\thispagestyle{title}
	\arrayrulecolor{gray25}
	
	\begin{flushleft}
		\huge \documentname
		\normalsize
	\end{flushleft}
	
	\section*{Revision History}
	The following table shows the revision history for this document. But also it shows how a full-width table may look like.
	
	
	\newpage
	\tableofcontents
	\newpage
	
	\section{General Description}
	This document shows possibilities of LaTeX for creating datasheets. 
	The most suitable use-case of this template is a relatively short datasheet of up to about 30 pages.
	Although this document shows some LaTeX commands, it cannot be used as a LaTeX tutorial.
	There are plenty of LaTeX tutorials on internet.
	
	\section{Insert figures}
	The best practice to keep your figures with the tex-file is putting them into \verb+/fig+ directory. 
	How your illustration may look like in a datasheet is shown in Figure \ref{fig:FigureRef}.
	\begin{figure}[H]
		\centering % \begin{center}/\end{center} takes some additional vertical space
		\includegraphics[width=10cm]{fig/SampleFigure.png}
		\caption{This is a caption of an example figure. An AI-generated abstract figure was used for the illustrative purpose.}
		\label{fig:FigureRef}
	\end{figure}
	
	
	\section{Sections and subsections}
	
	\subsection{Document hierarchy}
	Like in all LaTeX documents you can introduce hierarchy in your datasheets. 
	For most cases two hierarchical levels are enough. 
	In order to introduce them in your document use the \verb+\section+ and \verb+\subsection+ commands. 
	
	
	
	\subsection{Code entries}
	If insertion of a code snippet with a monospaced font is needed, use the verbatim sections and include your code between \verb+\begin{verbatim}+ and \verb+\end{verbatim}+ commands. 
	Here is an example:
	\begin{verbatim}
		COMPONENT yet_another_VHDL_component
		GENERIC(
		top_clk_freq        : INTEGER := 40_000_000; 
		i2_clk_freq         : INTEGER := 100_000;      
		Polling_freq        : INTEGER := 4);
		PORT (
		sysclk              : in STD_LOGIC;
		reset_n             : in STD_LOGIC;
		data_regs           : out t_data_regs;
		control_reg         : in std_logic_vector;
		i2c_sda             : inout STD_LOGIC;  
		i2c_scl             : inout STD_LOGIC   
		);
		END COMPONENT;
	\end{verbatim}
	
	%\begin{tikzpicture}
	%	\begin{axis}[xlabel=2014\hspace{3cm} 2015\hspace{3cm} 2016,axis x line=bottom,
		%		axis y line=left,enlarge x limits=0.01,enlarge y limits=0.003,thick,ylabel=月接待游客数量（万人）,ymin=15,ymax=46,symbolic x coords={0,4-1,4-2,4-3,4-4,4-5,4-6,4-7,4-8,4-9,4-10,4-11,4-12,5-1,5-2,5-3,5-4,5-5,5-6,5-7,5-8,5-9,5-10,5-11,5-12,
			%			6-1,6-2,6-3,6-4,6-5,6-6,6-7,6-8,6-9,6-10,6-11,6-12},
		%		x tick label style={
			%			rotate=90,
			%			font=\tiny
			%		},
		%		ylabel style={xshift=-2mm,yshift=0mm},
		%		xlabel style={xshift=0mm,yshift=2mm},
		%		y tick label style={
			%			rotate=0,
			%			font=\small
			%		},
		%		xtick distance=1,
		%		ytick distance=5,
		%		ytick align=inside,
		%		xtick align=inside,
		%		tick style={black,thick},
		%		width=14cm,
		%		height=6cm,
		%		minor ytick={20,25,30,35,40,45},
		%		grid=minor,
		%		grid style={thick,black,dashed},
		%		]
		%		\addplot+ table[mark=square*,x=xdata,y=ydata] {
			%			xdata ydata
			%			4-1 22
			%			4-2 24
			%			4-3 24
			%			4-4 27
			%			4-5 27
			%			4-6 27
			%			4-7 33
			%			4-8 35
			%			4-9 30
			%			4-10 32.5
			%			4-11 29
			%			4-12 22.5
			%			5-1 30.5
			%			5-2 32
			%			5-3 31
			%			5-4 33
			%			5-5 33
			%			5-6 31
			%			5-7 36
			%			5-8 37.5
			%			5-9 34
			%			5-10 35
			%			5-11 32.5
			%			5-12 31.5
			%			6-1 32.5
			%			6-2 36
			%			6-3 37.5
			%			6-4 37
			%			6-5 36.5
			%			6-6 34
			%			6-7 39
			%			6-8 42.5
			%			6-9 37
			%			6-10 38
			%			6-11 30.6
			%			6-12 30.6
			%		};
		%	\end{axis}
	%\end{tikzpicture}
	
	
	\begin{tikzpicture}
		\begin{axis}
			\addplot+[smooth]                    % 设置绘图的类型是光滑线图
			coordinates
			{
				(0,4) (1,1) (2,2)
				(3,5) (4,6) (5,1)
			};
		\end{axis}
	\end{tikzpicture}
	
	
	\begin{tikzpicture}
		\begin{axis}[legend pos=outer north east] % 将图例放在图外，位于图的东北角
			\addplot 
			table                               % 绘制原始数据的折线图
			{           		                % X，Y的原始数据
				X Y
				1 1
				2 4
				3 9
				4 16 
				5 25
				6 36
			};
			\addplot
			table[y={create col/linear regression={y=Y}}] % 对输入的数据作线性回归
			{   				
				X Y
				1 1
				2 4
				3 9
				4 16 
				5 25
				6 36
			};
			\addlegendentry{$y(x)$}          % 给第一个图像添加图例，即原始函数y(x)
			\addlegendentry{                 % 给第二个图像添加图例，即线性回归结果a*x+b
				$\pgfmathprintnumber{\pgfplotstableregressiona} \cdot x
				\pgfmathprintnumber[print sign]{\pgfplotstableregressionb}$}
		\end{axis}
	\end{tikzpicture}
	
	
	
	\begin{center}
		\label{tab:flash_ecc_err_pos}
		\captionof{table}{Flash ECC error bit and position.}
		\tablefirsthead{   \hline
			\textbf{Pos} & \textbf{SYND7} & \textbf{SYND6} & \textbf{SYND5} & \textbf{SYND4} & \textbf{SYND3} & \textbf{SYND2} & \textbf{SYND1} & \textbf{SYND0} & \textbf{SYND} \\ \chline
			\hline}
		\tablehead{   \hline
			\textbf{Pos} & \textbf{SYND7} & \textbf{SYND6} & \textbf{SYND5} & \textbf{SYND4} & \textbf{SYND3} & \textbf{SYND2} & \textbf{SYND1} & \textbf{SYND0} & \textbf{SYND} \\ \chline
			\hline}
		\tabletail{%
			\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|c|c|c|c|c|c|c|}
			\hline
			\hline 71 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0x80 \\
			\hline 70 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0x40 \\
			\hline 69 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0x20 \\
			\hline 68 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0x10 \\
			\hline 67 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0x08 \\
			\hline 66 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0x04 \\
			\hline 65 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0x02 \\
			\hline 64 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0x01 \\
			\hline 63 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0xA4 \\
			\hline 62 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0xC4 \\
			\hline 61 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0xC2 \\
			\hline 60 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0xA2 \\
			\hline 59 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0x9E \\
			\hline 58 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0xC1 \\
			\hline 57 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0xA1 \\
			\hline 56 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0x91 \\
			\hline 55 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 0x52 \\
			\hline 54 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0x62 \\
			\hline 53 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0x61 \\
			\hline 52 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0x51 \\
			\hline 51 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 1 & 0x4F \\
			\hline 50 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0xE0 \\
			\hline 49 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0xD0 \\
			\hline 48 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0xC8 \\
			\hline 47 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0x29 \\
			\hline 46 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0x31 \\
			\hline 45 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0xB0 \\
			\hline 44 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0xA8 \\
			\hline 43 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 1 & 0xA7 \\
			\hline 42 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0x70 \\
			\hline 41 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0x68 \\
			\hline 40 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0x64 \\
			\hline 39 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0x94 \\
			\hline 38 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0x98 \\
			\hline 37 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0x58 \\
			\hline 36 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0x54 \\
			\hline 35 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & 0xD3 \\
			\hline 34 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0x38 \\
			\hline 33 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0x34 \\
			\hline 32 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0x32 \\
			\hline 31 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 0x4A \\
			\hline 30 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0x4C \\
			\hline 29 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 0 & 0x2C \\
			\hline 28 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 0x2A \\
			\hline 27 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 0xE9 \\
			\hline 26 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0x1C \\
			\hline 25 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0x1A \\
			\hline 24 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 0x19 \\
			\hline 23 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0x25 \\
			\hline 22 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0x26 \\
			\hline 21 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 0x16 \\
			\hline 20 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0x15 \\
			\hline 19 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0xF4 \\
			\hline 18 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0x0E \\
			\hline 17 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0x0D \\
			\hline 16 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0x8C \\
			\hline 15 & 1 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0x92 \\
			\hline 14 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0x13 \\
			\hline 13 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 0x0B \\
			\hline 12 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0x8A \\
			\hline 11 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0x7A \\
			\hline 10 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0x07 \\
			\hline 9 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0x86 \\
			\hline 8 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0x46 \\
			\hline 7 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 & 0x49 \\
			\hline 6 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0x89 \\
			\hline 5 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0x85 \\
			\hline 4 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0x45 \\
			\hline 3 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0x3D \\
			\hline 2 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0x83 \\
			\hline 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 0x43 \\
			\hline 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0x23 \\
			
			\hline
		\end{xtabular}
	\end{center}
	
	
	\section{GPIO}
	aa
	\subsection{Registers}
\subsubsection{MODER}
Address: 0x400F0000. Reset: 0x0000A03F
\newline 
GPIO Mode Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:10 & MODE5 & WR & GPIO5 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        9:8 & MODE4 & WR & GPIO4 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        7:6 & MODE3 & WR & GPIO3 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        5:4 & MODE2 & WR & GPIO2 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: ALTERNATE\newline 3: ANALOG\\ \hline
        3:2 & MODE1 & WR & GPIO1 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: Reserve\newline 3: ANALOG\\ \hline
        1:0 & MODE0 & WR & GPIO0 supports four modes, which can be\newline 0: INPUT\newline 1: OUTPUT\newline 2: Reserve\newline 3: ANALOG\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{STR}
Address: 0x400F0004. Reset: 0x00000000
\newline 
GPIO Strength Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & ST7 & WR & GPIO7 strength configration\newline 0: OHM67. 67ohm. \newline 1: OHM57. 57ohm.\\ \hline
        6:6 & ST6 & WR & GPIO6 strength configration, as descripted in STR7.\\ \hline
        5:5 & ST5 & WR & GPIO5 strength configration, as descripted in STR7.\\ \hline
        4:4 & ST4 & WR & GPIO4 strength configration, as descripted in STR7.\\ \hline
        3:3 & ST3 & WR & GPIO3 strength configration, as descripted in STR7.\\ \hline
        2:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SLEWR}
Address: 0x400F0008. Reset: 0x00000000
\newline 
GPIO SLEW Rate Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & RATE7 & WR & GPIO7 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        6:6 & RATE6 & WR & GPIO6 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        5:5 & RATE5 & WR & GPIO5 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        4:4 & RATE4 & WR & GPIO4 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        3:3 & RATE3 & WR & GPIO3 slew rate, which can be \newline 0: NS4. 4ns \newline 1: NS5. 5ns\\ \hline
        2:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PUPDR}
Address: 0x400F000C. Reset: 0x00009540
\newline 
GPIO Pull-up/Pull-down Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:16 & Reserve & RO & Reserve.\\ \hline
        15:14 & PUPD7 & WR & GPIO7 Pull-up/Pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        13:12 & PUPD6 & WR & GPIO6 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        11:10 & PUPD5 & WR & GPIO5 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        9:8 & PUPD4 & WR & GPIO4 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        7:6 & PUPD3 & WR & GPIO3 pull-up/pull-down selection can be\newline 0: None\newline 1: PullUp\newline 2: PullDown\\ \hline
        5:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IDR}
Address: 0x400F0010. Reset: 0x000000FF
\newline 
GPIO Input Data Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:6 & Reserve & RO & Reserve.\\ \hline
        5:5 & ID5 & RO & If MODER5 is INPUT, this bit reflects the external voltage level on GPIO5.\\ \hline
        4:4 & ID4 & RO & If MODER4 is INPUT, this bit reflects the external voltage level on GPIO4.\\ \hline
        3:3 & ID3 & RO & If MODER3 is INPUT, this bit reflects the external voltage level on GPIO3.\\ \hline
        2:2 & ID2 & RO & If MODER2 is INPUT, this bit reflects the external voltage level on GPIO2.\\ \hline
        1:1 & ID1 & RO & If MODER1 is INPUT, this bit reflects the external voltage level on GPIO1.\\ \hline
        0:0 & ID0 & RO & If MODER0 is INPUT, this bit reflects the external voltage level on GPIO0.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ODR}
Address: 0x400F0014. Reset: 0x00000000
\newline 
GPIO Output Data Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:6 & Reserve & RO & Reserve.\\ \hline
        5:5 & OD5 & WR & If MODER5 is OUTPUT, this bit sets the output voltage level of GPIO5.\\ \hline
        4:4 & OD4 & WR & If MODER4 is OUTPUT, this bit sets the output voltage level of GPIO4.\\ \hline
        3:3 & OD3 & WR & If MODER3 is OUTPUT, this bit sets the output voltage level of GPIO3.\\ \hline
        2:2 & OD2 & WR & If MODER2 is OUTPUT, this bit sets the output voltage level of GPIO2.\\ \hline
        1:1 & OD1 & WR & If MODER1 is OUTPUT this bit sets the output voltage level of GPIO1.\\ \hline
        0:0 & OD0 & WR & If MODER0 is OUTPUT, this bit sets the output voltage level of GPIO0.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{AFR}
Address: 0x400F0020. Reset: 0x00000000
\newline 
GPIO Alternate Function Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & Reserve & RO & Reserve.\\ \hline
        23:20 & AF5 & WR & Alternate selection for GPIO5, which can be\newline 0: Reserve0\newline 1: Reserve1\newline 2: Reserve2\newline 3: TIM\_OC\_CH1. This signal toggles at the monment of TIM0 count overflowing.\newline 4: PWM\_OC\_CH1. This signal toggles at the monment of LEDCTRL count overflowing.\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        19:16 & AF4 & WR & Alternate selection for GPIO4, which can be\newline 0: Reserve0\newline 1: LINCRX\_LINPHYTX. This signal can be LINC RX or LINS/LINM TX, depending on the TBD. \newline 2: LINCRX\_MONITOR. This signal reprensents LINC RX when TBD.\newline 3: TIM\_OC\_CH1. This signal toggles at the monment of TIM0 count overflowing.\newline 4: PWM\_OC\_CH1. This signal toggles at the monment of LEDCTRL count overflowing.\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        15:12 & AF3 & WR & Alternate selection for GPIO3, which can be\newline 0: RCC\_CLK. This signal can be system clock / 64 or slow 256KHz clock.\newline 1: LINCTX\_LINPHYRX. This signal can be LINC TX or LINS/LINM RX, depending on the TBD\newline 2: LINCTX\_MONITOR. This signal reprensents LINC TX when TBD.\newline 3: TIM\_OC\_CH0. This signal toggles at the monment of TIM0 count overflowing.\newline 4: PWM\_OC\_CH0. This signal toggles at the monment of LEDCTRL count overflowing.\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        11:8 & AF2 & WR & Alternate selection for GPIO2, which can be\newline 0: LEDCTRL\_CH2. This signal will be high, when LED2 current is turn on. This signal will be low, when LED2 current is turn off.\newline 1: RCC\_CLK. This signal can be system clock / 64 or slow 512KHz clock.\newline 2: Reserve2\newline 3: Reserve3\newline 4: Reserve4\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        7:4 & AF1 & WR & Alternate selection for GPIO1, which can be\newline 0: LEDCTRL\_CH1. This signal will be high, when LED1 current is turn on. This signal will be low, when LED1 current is turn off.\newline 1: Reserve1\newline 2: Reserve2\newline 3: Reserve3\newline 4: Reserve4\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
        3:0 & AF0 & WR & Alternate  selection for GPIO0, which can be\newline 0: LEDCTRL\_CH0. This signal will be high, when LED0 current is turn on. This signal will be low, when LED0 current is turn off.\newline 1: Reserve1\newline 2: Reserve2\newline 3: Reserve3\newline 4: Reserve4\newline 5: Reserve5\newline 6: Reserve6\newline 7: Reserve7\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{EER}
Address: 0x400F002C. Reset: 0x00000000
\newline 
GPIO risr/fall edge enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & FE5 & WR & Enable GPIO5 fall edge enable\newline 0: DIS. Disable detecting GPIO5 fall.\newline 1: EN. Enable detecting GPIO5 fall.\\ \hline
        21:21 & RE5 & WR & Enable GPIO5 rise edge enable\newline 0: DIS. Disable detecting GPIO5 rise.\newline 1: EN. Enable detecting GPIO5 rise.\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & FE4 & WR & Enable GPIO4 fall edge enable\newline 0: DIS. Disable detecting GPIO4 fall.\newline 1: EN. Enable detecting GPIO4 fall.\\ \hline
        17:17 & RE4 & WR & Enable GPIO4 rise edge enable\newline 0: DIS. Disable detecting GPIO4 rise.\newline 1: EN. Enable detecting GPIO4 rise.\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & FE3 & WR & Enable GPIO3 fall edge enable\newline 0: DIS. Disable detecting GPIO3 fall.\newline 1: EN. Enable detecting GPIO3 fall.\\ \hline
        13:13 & RE3 & WR & Enable gpio3 rise edge enable\newline 0: DIS. Disable detecting GPIO3 rise.\newline 1: EN. Enable detecting GPIO3 rise.\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{IER}
Address: 0x400F0030. Reset: 0x00000000
\newline 
GPIO Interrupt Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & FI5 & WR & Enable GPIO5 fall edge interrupt\newline 0: DIS. Disable GPIO5 fall interrupt.\newline 1: EN. Enable GPIO5 fall interrupt.\\ \hline
        21:21 & RI5 & WR & Enable GPIO5 rise edge interrupt\newline 0: DIS. Disable GPIO5 rise interrupt.\newline 1: EN. Enable GPIO5 rise interrupt.\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & FI4 & WR & Enable GPIO4 fall edge interrupt\newline 0: DIS. Disable GPIO4 fall interrupt.\newline 1: EN. Enable GPIO4 fall interrupt.\\ \hline
        17:17 & RI4 & WR & Enable GPIO4 rise edge interrupt\newline 0: DIS. Disable GPIO4 rise interrupt.\newline 1: EN. Enable GPIO4 rise interrupt.\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & FI3 & WR & Enable GPIO3 fall edge interrupt\newline 0: DIS. Disable GPIO3 fall interrupt.\newline 1: EN. Enable GPIO3 fall interrupt.\\ \hline
        13:13 & RI3 & WR & Enable GPIO3 rise edge interrupt\newline 0: DIS. Disable GPIO3 rise interrupt.\newline 1: EN. Enable GPIO3 rise interrupt.\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ESR}
Address: 0x400F0034. Reset: 0x00000000
\newline 
GPIO Interrupt Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & F5F & RO & GPIO5 fall edge flag\\ \hline
        21:21 & R5F & RO & GPIO5 rise edge flag\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & F4F & RO & GPIO4 fall edge flag\\ \hline
        17:17 & R4F & RO & GPIO4 rise edge flag\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & F3F & RO & GPIO3 fall edge flag\\ \hline
        13:13 & R3F & RO & GPIO3 rise edge flag\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ESCLR}
Address: 0x400F0038. Reset: 0x00000000
\newline 
GPIO Intterupt Status Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:22 & F5CLR & WO & Writing 1 clear GPIO5 fall edge flag.\\ \hline
        21:21 & R5CLR & WO & Writing 1 clear GPIO5 rise edge flag.\\ \hline
        20:19 & Reserve & RO & Reserve.\\ \hline
        18:18 & F4CLR & WO & Writing 1 clear GPIO4 fall edge flag.\\ \hline
        17:17 & R4CLR & WO & Writing 1 clear GPIO4 rise edge flag.\\ \hline
        16:15 & Reserve & RO & Reserve.\\ \hline
        14:14 & F3CLR & WO & Writing 1 clear GPIO3 fall edge flag.\\ \hline
        13:13 & R3CLR & WO & Writing 1 clear GPIO3 rise edge flag.\\ \hline
        12:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

	\section{SYSCTRL}
	bb
	\subsection{Registers}
\subsubsection{CHIPIDR}
Address: 0x40001000. Reset: 0x25290111
\newline 
Chip ID Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & VAL & RO & Chip Identification.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RDPR}
Address: 0x40001020. Reset: 0x00000000
\newline 
FLASH Read Protect Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & RDP & WR & Read Protect Enable Register.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMIER}
Address: 0x40001100. Reset: 0x00000000
\newline 
RAM ECC Interrupt Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & RAMECC & WR & RAM ECC Interrupt Enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMSR}
Address: 0x40001104. Reset: 0x00000000
\newline 
RAM ECC Interrupt Status Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:0 & ERR & RO & When read RAM, ECC detects 1 bit err in one word, and correct this err bit.\newline 0: NOERR. No ecc err. \newline 1: ERR1B. When read RAM, ECC detects 1 bit err, and correct this err bit. \newline 2: ERR2B. When read RAM, ECC detects 2 bit err.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMSCLR}
Address: 0x40001108. Reset: 0x00000000
\newline 
RAM ECC Interrupt Status Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & ERRCLR & WO & Write 1 clear RAMECCSR.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMSYNDR}
Address: 0x40001110. Reset: 0x00000000
\newline 
RAM ECC Syndrome Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:7 & Reserve & RO & Reserve.\\ \hline
        6:0 & SYND & RO & ECC Syndrome, There are RAM ECC err if this val is not 0. Use syndrome can find witch bit err if RAMCCSR is 1;\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMINJLR}
Address: 0x40001114. Reset: 0x00000000
\newline 
RAM ECC Inject Low Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:0 & INJL & WR & Note: only when DBGEN = 1, writing this value is effective. When this val is not 0, read ram will lead to ecc error. For example, if this value is 0x8, read ram will lead to 4th ram Bit error.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RAMINJHR}
Address: 0x40001118. Reset: 0x00000000
\newline 
RAM ECC Interrupt Status Clear Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:7 & Reserve & RO & Reserve.\\ \hline
        6:0 & INJH & WR & Note: only when DBGEN = 1, writing this value is effective. When this val is not 0, read ram will lead to ecc error. For example, if this value is 0x8, read ram will lead to 36th ram Bit error.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{ADCTGSRCR}
Address: 0x40001200. Reset: 0x00000000
\newline 
ADC trig source select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & adc trig select source.\newline 0: NOTG. No event trig\newline 1: PWM0TG. PWM0 event trig\newline 2: PWM1TG. PWM1 event trig\newline 3: PWM2TG. PWM2 event trig\newline 4: PWMALLTG. Any PWM event trig\newline 5: TIM0TG. TIM0 event trig\newline 6: TIM1TG. TIM1 event trig\newline 7: TIM2TG. TIM2 event trig\newline 8: PWM\_OVERFLOW\_TRG. PWM period overflow event trig\newline 9: GPIO3TG. GPIO3 input rise/fall edge event trig\newline 10: GPIO4TG. GPIO4 input rise/fall edge event trig\newline 11: GPIO5TG. GPIO5 input rise/fall edge event trig\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TIM0TGSRCR}
Address: 0x40001204. Reset: 0x00000000
\newline 
TIM0 trig select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & tim0 trig select source.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TIM1TGSRCR}
Address: 0x40001208. Reset: 0x00000000
\newline 
TIM1 trig select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & tim1 trig select source.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{TIM2TGSRCR}
Address: 0x4000120C. Reset: 0x00000000
\newline 
TIM2 trig select Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & TGSRC & WR & tim2 trig select source.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DBGER}
Address: 0x40001E00. Reset: 0x00000000
\newline 
Debug Enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DFT EN key. To write DBGEN, this field must be 0xA5.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & EN & WR & Only when KEY is matched and DBGLOCK LOCK(bit0) is 0, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DBGLOCKR}
Address: 0x40001E04. Reset: 0x00000001
\newline 
DBG Lock Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DBG LOCK key. To write DBGLOCK, this field must be 0x5A.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & LOCK & WR & Only when KEY is matched, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DBGMODE\_RES}
Address: 0x40001E08. Reset: 0x00000000
\newline 
DBG MODE register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:0 & MODE & WR & Select DBG mode, and start DBG test.\newline 0: NONE\newline 1: LEDDRV. LEDDRV debug test.\newline 2: ADC. ADC debug test.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DFTER\_RES}
Address: 0x40001F00. Reset: 0x00000000
\newline 
DFT Enable Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DFT EN key. To write DFTEN, this field must be 0xA5.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & EN & WR & Only when KEY is matched and DFTLOCK LOCK(bit0) is 0, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DFTLOCKR\_RES}
Address: 0x40001F04. Reset: 0x00000001
\newline 
DFT Lock Register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WO & DFT LOCK key. To write DFTLOCK, this field must be 0x5A.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & LOCK & WR & Only when KEY is matched, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{DFTMODER\_RES}
Address: 0x40001F08. Reset: 0x00000000
\newline 
DFT MODE register 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & MODE & WR & Select DTF mode, and start DFT test.\newline 0x3: SCAN. Scan test.\newline 0x5: RAMBIST. Ram bist test.\newline 0xA: FLSBIST. Flash bist test.\\ \hline
		\end{xtabular}
	\end{center}

	\section{RCC}
cc
\subsection{Registers}
\subsubsection{CLKDIVR}
Address: 0x40003000. Reset: 0x00000004
\newline 
System Clock Divider Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & CLKDIV & WR & System clock dividor. SysClk = 32MHz / CLKDIV\newline 1: DIV2\newline 2: DIV4\newline 3: DIV6\newline 4: DIV8\newline 5: DIV10\newline 6: DIV12\newline 7: DIV14\newline 8: DIV16\newline 9: DIV18\newline 10: DIV20\newline 11: DIV22\newline 12: DIV24\newline 13: DIV26\newline 14: DIV28\newline 15: DIV30\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PERICLKER}
Address: 0x40003004. Reset: 0x000001E2
\newline 
Peripheral Clock Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & GPIO & WR & GPIO module clock enable.\\ \hline
        7:7 & ADCCTRL & WR & ADCCTRL module clock enable.\\ \hline
        6:6 & LEDCTRL & WR & LEDCTRL module clock enable.\\ \hline
        5:5 & SYSCTRL & WR & SYSCTRL module clock enable.\\ \hline
        4:4 & TIM0 & WR & TIM0 module clock enable.\\ \hline
        3:3 & TIM1 & WR & TIM1 module clock enable.\\ \hline
        2:2 & TIM2 & WR & TIM2 module clock enable.\\ \hline
        1:1 & LIN & WR & LINCTRL module clock enable.\\ \hline
        0:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SYSRSTR}
Address: 0x40003100. Reset: 0x00000000
\newline 
System Reset Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:24 & KEY & WR & The SYSRST bit protection KEY.\\ \hline
        23:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & SYSRST & WR & System reset. Only when KEY is 0x5A, writing this bit is effective.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{PERIRSTR}
Address: 0x40003104. Reset: 0x00000000
\newline 
Peripheral Reset Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:9 & Reserve & RO & Reserve.\\ \hline
        8:8 & GPIO & WR & GPIO module reset.\newline 0: RST\_RELEASE. Release GPIO module reset state.\newline 1: RST\_HOLD. Hold GPIO module reset state.\\ \hline
        7:7 & ADCCTRL & WR & ADCCTRL module reset.\newline 0: RST\_RELEASE. Release ADCCTRL module reset state.\newline 1: RST\_HOLD. Hold ADCCTRL module reset state.\\ \hline
        6:6 & LEDCTRL & WR & LEDCTRL module reset.\newline 0: RST\_RELEASE. Release LEDCTRL module reset state.\newline 1: RST\_HOLD. Hold LEDCTRL module reset state.\\ \hline
        5:5 & SYSCTRL & WR & SYSCTRL module reset.\newline 0: RST\_RELEASE. Release SYSCTRL module reset state.\newline 1: RST\_HOLD. Hold SYSCTRL module reset state.\\ \hline
        4:4 & TIM0 & WR & TIM0 module reset.\newline 0: RST\_RELEASE. Release TIM0 module reset state.\newline 1: RST\_HOLD. Hold TIM0 module reset state.\\ \hline
        3:3 & TIM1 & WR & TIM1 module reset.\newline 0: RST\_RELEASE. Release TIM1 module reset state.\newline 1: RST\_HOLD. Hold TIM1 module reset state.\\ \hline
        2:2 & TIM2 & WR & TIM2 module reset.\newline 0: RST\_RELEASE. Release TIM2 module reset state.\newline 1: RST\_HOLD. Hold TIM2 module reset state.\\ \hline
        1:1 & LIN & WR & LINCTRL module reset.\newline 0: RST\_RELEASE. Release LINCTRL module reset state.\newline 1: RST\_HOLD. Hold LINCTRL module reset state.\\ \hline
        0:0 & Reserve & RO & Reserve.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{RSTFR}
Address: 0x40003108. Reset: 0x00000001
\newline 
Reset Flag Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:4 & Reserve & RO & Reserve.\\ \hline
        3:0 & RSTF & RO & Indicate the last reset source.\newline 0x0: None. No reset event.\newline 0x1: POR. Power on reset.\newline 0x2: WWDG. WWDG timeout reset.\newline 0x3: SYSRST. Reset by setting SYSRSTR.SYSRST.\newline 0x4: CORERST. CPU core reset.\newline 0x5: VBATUV. Battery voltage under threshold reset.\newline 0x6: VBATOV. Battery voltage over threshold reset.\newline 0x7: OTW. Temperature measured by ADC over threshold reset.\newline 0x8: LDO50OV. LDO50 voltage over monitor threshold reset.\newline 0x9: LDO50UV. LDO50 voltage under monitor threshold reset.\newline 0xA: LDO15OV. LDO15 voltage over monitor threshold reset.\newline 0xB: LDO15UV. LDO15 voltage under monitor threshold reset.\newline 0xC: OTP. Temperature over monitor threshold reset.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LDO15MONR}
Address: 0x40003110. Reset: 0x00000880
\newline 
LDO15 Monitor Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & OVTH & WR & Selects the reference level for LDO1P5 over threshold monitor. \newline range: 1.52V~1.82V.\newline default : 0x8, Vrise = 1.65V, hysteresis = 50mV.\\ \hline
        7:4 & UVTH & WR & Selects the reference level for LDO1P5 under threshold monitor. \newline range: 1.18V~1.65V.\newline default : 0x8, Vrise = 1.35V, hysteresis = 50mV.\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & OVEN & WR & LDO 1.5V voltage over threshold monitor enable.\\ \hline
        0:0 & UVEN & WR & LDO 1.5V voltage under threshold monitor enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATMONR}
Address: 0x40003114. Reset: 0x00082130
\newline 
VBAT Monitor Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & Reserve & RO & Reserve.\\ \hline
        19:16 & OVTH & WR & Battery voltage over threshold. The following table is based on OVHYS is set to 0.\newline 0x0: Vrise:14.29, Vfall:14.07,hysteresis:220mV;\newline 0x1: Vrise:14.74, Vfall:14.51,hysteresis:230mV;\newline 0x2: Vrise:14.98, Vfall:14.22,hysteresis:240mV;\newline 0x3: Vrise:15.73, Vfall:14.47,hysteresis:260mV;\newline 0x4: Vrise:16.30, Vfall:16.02,hysteresis:280mV;\newline 0x5: Vrise:16.90, Vfall:16.58,hysteresis:320mV;\newline 0x6: Vrise:17.54, Vfall:17.22,hysteresis:320mV;\newline 0x7: Vrise:18.24, Vfall:17.90,hysteresis:360mV;\newline 0x8: Vrise:19.04, Vfall:18.64,hysteresis:400mV; (Default)\newline 0x9: Vrise:19.44, Vfall:19.87,hysteresis:440mV;\newline 0xA: Vrise:20.80, Vfall:20.32,hysteresis:480mV;\newline 0xB: Vrise:21.82, Vfall:21.29,hysteresis:530mV;\newline 0xC: Vrise:22.97, Vfall:22.39,hysteresis:590mV;\newline 0xD: Vrise:24.24, Vfall:23.58,hysteresis:660mV;\newline 0xE: Vrise:25.67, Vfall:24.93,hysteresis:740mV;\newline 0xF: Vrise:27.28, Vfall:26.44,hysteresis:840mV.\\ \hline
        15:15 & Reserve & RO & Reserve.\\ \hline
        14:13 & OVHYS & WR & Battery voltage over threshold hysteresis. The following data is based on OVTH is set to 0x8.\newline 0: L0\_0P40. 0.40V\newline 1: L1\_1P02. 1.02V\newline 2: L2\_1P69. 1.69V\newline 3: L3\_2P37. 2.37V\\ \hline
        12:12 & OVEN & WR & Battery voltage over threshold monitor enable.\\ \hline
        11:10 & Reserve & RO & Reserve.\\ \hline
        9:8 & UVHYS & WR & Battery voltage under threshold hysteresis. The following data is based on UVTH is set to 0x3.\newline 0: L0\_0P08. 0.08V\newline 1: L1\_0P19. 0.19V\newline 2: L2\_0P28. 0.28V\newline 3: L3\_0P36. 0.36V\\ \hline
        7:4 & UVTH & WR & Battery voltage under threshold. The following table is based on UVHYS is set to 1.\newline 0x0: Vrise:5.00, Vfall:5.15,hysteresis:150mV;\newline 0x1: Vrise:5.14, Vfall:5.30,hysteresis:160mV;\newline 0x2: Vrise:5.31, Vfall:5.49,hysteresis:180mV;\newline 0x3: Vrise:5.48, Vfall:5.67,hysteresis:200mV; (Default)\newline 0x4: Vrise:5.68, Vfall:5.88,hysteresis:220mV;\newline 0x5: Vrise:5.88, Vfall:6.11,hysteresis:230mV;\newline 0x6: Vrise:6.11, Vfall:6.36,hysteresis:250mV;\newline 0x7: Vrise:6.36, Vfall:6.64,hysteresis:280mV;\newline 0x8: Vrise:6.61, Vfall:6.92,hysteresis:310mV; \newline 0x9: Vrise:6.91, Vfall:7.26,hysteresis:350mV;\newline 0xA: Vrise:7.26, Vfall:7.65,hysteresis:400mV;\newline 0xB: Vrise:7.64, Vfall:8.09,hysteresis:450mV;\newline 0xC: Vrise:8.10, Vfall:8.62,hysteresis:520mV;\newline 0xD: Vrise:8.60, Vfall:9.20,hysteresis:600mV;\newline 0xE: Vrise:9.20, Vfall:9.90,hysteresis:700mV;\newline 0xF: Vrise:9.88, Vfall:10.72,hysteresis:840mV.\\ \hline
        3:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & UVEN & WR & Battery voltage under threshold monitor enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{LDO50MONR}
Address: 0x40003118. Reset: 0x00000880
\newline 
LDO 5V Monitor Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & OVTH & WR & Selects the reference level for LDO1P5 over threshold monitor. \newline range: 5.2V~6.8V.\newline default : 0x8, Vrise = 6V, hysteresis = 190mV.\\ \hline
        7:4 & UVTH & WR & Selects the reference level for LDO1P5 under threshold monitor. \newline range: 3.6V~4.7V.\newline default : 0x8, Vrise = 4V, hysteresis = 220mV.\\ \hline
        3:2 & LDO50MEASEN & WR & LDO 5V measure enable. Only when this bit is set can ADC measures LDO 5V.\\ \hline
        1:1 & OVEN & WR & LDO 5V voltage over threshold monitor enable.\\ \hline
        0:0 & UVEN & WR & LDO 5V voltage under threshold monitor enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{OTPR}
Address: 0x4000311C. Reset: 0x00000080
\newline 
Over Temperature Protection Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:4 & OTPTH & WR & Select over-temperature threshold for OTP.\newline Default: Rising:155.4C, Falling: 136.4C, hysteresis: 20C\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & BGBFEN & WR & BandGap Buffer Enable. Before using temperature sensor, set this bit.\\ \hline
        0:0 & OTPEN & WR & Over Temperature Protection Enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFRSTER}
Address: 0x40003120. Reset: 0x00000000
\newline 
Safty Reset Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:8 & Reserve & RO & Reserve.\\ \hline
        7:7 & OTP & WR & Setting this bit will lead to system reset if OTP event is deteced by over-temperature monitor.\\ \hline
        6:6 & LDO50UV & WR & Setting this bit will lead to system reset if LDO5V voltage is under monitor threshold.\\ \hline
        5:5 & LDO50OV & WR & Setting this bit will lead to system reset if LDO5V voltage is over monitor threshold.\\ \hline
        4:4 & OTW & WR & Setting this bit will lead to system reset if OTW event is deteced by ADC.\\ \hline
        3:3 & LDO15UV & WR & Setting this bit will lead to system reset if LDO1V5 voltage is under monitor threshold.\\ \hline
        2:2 & LDO15OV & WR & Setting this bit will lead to system reset if LDO1V5 voltage is over monitor threshold.\\ \hline
        1:1 & VBATUV & WR & Setting this bit will lead to system reset if battery voltage is under monitor threshold.\\ \hline
        0:0 & VBATOV & WR & Setting this bit will lead to system reset if battery voltage is over monitor threshold.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFIFR}
Address: 0x40003124. Reset: 0x00000000
\newline 
RCC Interrupt Flag Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & VBATUVQ & RO & Battey voltage under monitor threshold quick interrupt flag.\\ \hline
        8:8 & VBATOVQ & RO & Battey voltage over monitor threshold quick interrupt flag.\\ \hline
        7:7 & OTP & RO & Over temperature protection interrupt flag.\\ \hline
        6:6 & LDO50UV & RO & LDO50 voltage under monitor threshold interrupt flag.\\ \hline
        5:5 & LDO50OV & RO & LDO50 voltage over monitor threshold interrupt flag.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & LDO15UV & RO & LDO15 voltage under monitor threshold interrupt flag.\\ \hline
        2:2 & LDO15OV & RO & LDO15 voltage over threshold interrupt flag.\\ \hline
        1:1 & VBATUV & RO & Battery voltage under monitor threshold interrupt flag.\\ \hline
        0:0 & VBATOV & RO & Battery voltage over monitor threshold interrupt flag.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFIER}
Address: 0x40003128. Reset: 0x00000000
\newline 
RCC Interrupt Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & VBATUVQ & WR & Battery voltage under monitor threshold quick interrupt enable.\\ \hline
        8:8 & VBATOVQ & WR & Battery voltage over monitor threshold quick interrupt enable.\\ \hline
        7:7 & OTP & WR & Temperature monited over monitor threshold interrupt enable.\\ \hline
        6:6 & LDO50UV & WR & LDO50 voltage under monitor threshold interrupt enable.\\ \hline
        5:5 & LDO50OV & WR & LDO50 voltage over monitor threshold interrupt enable.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & LDO15UV & WR & LDO15 voltage under monitor threshold interrupt enable.\\ \hline
        2:2 & LDO15OV & WR & LDO15 voltage over monitor threshold interrupt enable.\\ \hline
        1:1 & VBATUV & WR & Battery voltage under monitor threshold interrupt enable.\\ \hline
        0:0 & VBATOV & WR & Battery voltage over monitor threshold interrupt enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SAFICLR}
Address: 0x4000312C. Reset: 0x00000000
\newline 
RCC Interrupt Flag Clear Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:10 & Reserve & RO & Reserve.\\ \hline
        9:9 & VBATUVQ & WO & Write 1 to clear VBATUVQIF.\\ \hline
        8:8 & VBATOVQ & WO & Write 1 to clear VBATOVQIF.\\ \hline
        7:7 & OTP & WO & Write 1 to clear OPTIF.\\ \hline
        6:6 & LDO50UV & WO & Write 1 to clear LDO50UVIF.\\ \hline
        5:5 & LDO50OV & WO & Write 1 to clear LDO50OVIF.\\ \hline
        4:4 & Reserve & RO & Reserve.\\ \hline
        3:3 & LDO15UV & WO & Write 1 to clear LDO15UVIF.\\ \hline
        2:2 & LDO15OV & WO & Write 1 to clear LDO15OVIF.\\ \hline
        1:1 & VBATUV & WO & Write 1 to clear VBATUVIF.\\ \hline
        0:0 & VBATOV & WO & Write 1 to clear VBATOVIF.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{BIASER}
Address: 0x40003130. Reset: 0x00000000
\newline 
BIAS Enable Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:1 & Reserve & RO & Reserve.\\ \hline
        0:0 & BIASEN & WR & Enable ibias.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{SSCR}
Address: 0x40003200. Reset: 0x00100810
\newline 
Spread Spectrum Clocking Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:23 & Reserve & RO & Reserve.\\ \hline
        22:16 & freq\_stay & WR & \\ \hline
        15:12 & Reserve & RO & Reserve.\\ \hline
        11:8 & freq\_range & WR & \\ \hline
        7:4 & freq\_step & WR & \\ \hline
        3:3 & en & WR & \\ \hline
        2:2 & Reserve & RO & Reserve.\\ \hline
        1:0 & mode & WR & 0: SawtoothUp\newline 1: SawtoothUpDown\newline 2: SawtoothDown\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{CLKDBGR}
Address: 0x40003180. Reset: 0x00000000
\newline 
Clock Debug Register. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & LINBAUDCLK\_RES & WR & \\ \hline
        0:0 & MCO & WR & Microcontroller clock output.\newline 0: RCOSC. High frequncy clock, which is diveded to 512KHz.\newline 1: LPOSC. Low frequncy 256KHz clock .\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATUVCR0}
Address: 0x40003204. Reset: 0x00100001
\newline 
Battery Under Threshold Debounce Control Register0. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & DBNCTHHQ & WR & Under voltage debounce quick threshold for 0to1 transition.\newline It will require the VBATUVQ event to stay low for (UVDBNCTH1Q + 1) system clock.\\ \hline
        19:18 & Reserve & RO & Reserve.\\ \hline
        17:0 & DBNCTHH & WR & Under voltage debounce threshold for 0to1 transition.\newline It will require the VBATUV event to stay low for (UVDBNCTH1 + 1) system clock.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATUVCR1}
Address: 0x40003208. Reset: 0x003FFFF0
\newline 
Battery Under Threshold Debounce Control Register1. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:22 & Reserve & RO & Reserve.\\ \hline
        21:4 & DBNCTHL & WR & Under voltage debounce threshold for 1to0 transition.\newline It will require the VBATUV event to stay high for (UVDBNCTH1 + 1) system clock.\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & UVQEN & WR & Batter under voltage detection enable.\\ \hline
        0:0 & UVEN & WR & Batter under voltage quick detection enable.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATOVCR0}
Address: 0x4000320C. Reset: 0x00100001
\newline 
Battery Over Threshold Debounce Control Register0. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:20 & DBNCTHHQ & WR & Under voltage debounce quick threshold for 0to1 transition.\newline It requires the VBATOVQ event to stay low for (OVDBNCTH1Q + 1) system clock.\\ \hline
        19:18 & Reserve & RO & Reserve.\\ \hline
        17:0 & DBNCTHH & WR & Under voltage debounce threshold for 0to1 transition.\newline It requires the VBATOV event to stay low for (OVDBNCTH1 + 1) system clock.\\ \hline
		\end{xtabular}
	\end{center}

\subsubsection{VBATOVCR1}
Address: 0x40003210. Reset: 0x003FFFF0
\newline 
Battery Over Threshold Debounce Control Register1. 
	\begin{center}
		\tablefirsthead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
			\hline}
		\tablehead{   \hline
		\textbf{Bits} & \textbf{Name} & \textbf{Access} & \textbf{Decription} \\ \chline
		\hline}
		\tabletail{%
    	\hline}
		\def\arraystretch{1.5}
		\begin{xtabular}{|c|c|c|p{11cm}|}
        31:22 & Reserve & RO & Reserve.\\ \hline
        21:4 & DBNCTHL & WR & Over voltage debounce threshold for 1to0 transition.\newline It requires the battery voltage falling below (VBATMONR.OVTH - VBATMONR.OVHYS) for at least(OVDBNCTHL + 1) system clock.\\ \hline
        3:2 & Reserve & RO & Reserve.\\ \hline
        1:1 & OVQEN & WR & Batter over voltage detection enable.\\ \hline
        0:0 & OVEN & WR & Batter over voltage quick detection enable.\\ \hline
		\end{xtabular}
	\end{center}

\end{document}t}nable.\\ \hline
		\end{xtabular}
	\end{center}

\end{document}t}t}t}ument}t}t}t}